The field of the invention is wafer level packaging on silicon substrates. More specifically, the field of the invention is wafer level packaging that uses through-silicon vias. In a preferred embodiment, the field of the invention is wafer level packaging for the production of sub-receivers and receivers for concentrator photovoltaic modules.
Metal-assisted chemical etching is known in the art for forming nanostructures in silicon by highly anisotropic etching. Examples include US Pat. Pub. Nos. 2011/0263119, 2013/0052762; U.S. Pat. Nos. 6,762,134, 6,790,785; Huang et al. Adv. Mater. 2011, 23, 285-309; Peng et al. Adv. Funct. Mater. 2008, 18, 3026-3035; Appl. Phys. Lett. 77(16) (2000): 2572-2574. US Pat. Pub. No. 2011/0263119 describes forming nanoscale patterns in a porous semiconductor. That study, however, is limited in terms of length scales and fundamentally relates to porous materials. In contrast, the invention provided herein desirably avoids porosity. Provided herein is metal-catalyzed chemical etching to form structures in silicon that extend from a top surface of the substrate to the bottom surface of the substrate that are suitable for electrical interconnects in wafer level packaging. In particular, there is a need for processes that etch at least a thickness of the substrate to form submounts and interposers for a variety of applications.